sphinxcontrib-verilog-diagrams 0.1.0

Required

• yosys

By default, verilog-diagram uses the yowasp-yosys package provided in PyPI. It can be installed by running pip install -r requirements.txt. However, you could also use Yosys that is installed on your system, or point to the specific Yosys binary using verilog_diagram_yosys variable in the Sphinx conf.py file:

To use Yosys that is available in your system, use the following setting:

verilog_diagram_yosys = "system"

If you want to point to the specific Yosys binary, provide the path to the program:

verilog_diagram_yosys = "<path-to-Yosys>"

Optional

• netlistsvg

Options

:type: - HDL Diagram Types;

• yosys-blackbox - Netlist rendered by Yosys.

• yosys-aig - Verilog file run through aigmap before image is generated directly in Yosys.

• netlistsvg - Render output with netlistsvg

:module: - Which module to diagram.

:flatten: - Use the Yosys flatten command before generating the image.

Example

Here is a diagram of a 4-bit carry chain.

Example

Here is a comparison between the literalinclude and no-license directives.

.. literalinclude:: verilog/dff.v
   :language: verilog
   :caption: verilog/dff.v

/*
 * Copyright (C) 2020  The SymbiFlow Authors.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

// Single flip-flip test.
module top(input clk, input di, output do);
  always @( posedge clk )
    do <= di;
endmodule // top

.. no-license:: verilog/dff.v
   :language: verilog
   :caption: verilog/dff.v

// Single flip-flip test.
module top(input clk, input di, output do);
  always @( posedge clk )
    do <= di;
endmodule // top